Digital Logic Design Designing Skid Buffers for Pipelines By chipmunk March 27, 2022 4 5 min read: What are Skid Buffers? How is it useful while designing elastic pipelines? How to design a Skid Buffer in Verilog / VHDL? Read on... Read more
IP Cores Displaying Videos with VGA Controller in Verilog / VHDL By chipmunk January 9, 2022 22 5 min read: Fancy displaying some colors and video patterns on your monitor with FPGA? Learn how to design a simple VGA Controller in RTL and get grasp on basics… Read more