Digital Logic Design Designing RISC-V CPU from scratch – Part 5: Decode Unit By chipmunk April 6, 2024 1 10 min read: Ever fancied designing your own processor but had no idea where to start with? Part-5 of RISC-V CPU Development blog series is here... Read more
Digital Logic Design White Papers Logic vs Wire in SV – some misconceptions By chipmunk February 9, 2024 2 5 min read: How do wire vs logic compare in System Verilog? What If I said it doesn't make any sense to compare them at all! Read on... Read more
Digital Logic Design Designing RISC-V CPU from scratch – Part 4: Fetch Unit By chipmunk December 9, 2023 7 10 min read: Ever fancied designing your own processor but had no idea where to start with? Part-4 of RISC-V CPU Development blog series is here... Read more
Digital Logic Design Designing RISC-V CPU from scratch – Part 3: Dealing with Pipeline Hazards By chipmunk July 8, 2023 4 5 min read: Ever fancied designing your own processor but had no idea where to start with? Part-3 of RISC-V CPU Development blog series is here... Read more