Let’s get a break from dealing with all those ‘invisible’ signals on board. A fun thing to do in RTL is to actually see and perceive something interesting with eyes, turn signals into visual form: Images and Videos. Playing around and understanding video interfacing on FPGAs is what this blog is about. The reader is expected to know basics of what is an image/video, terminolgies, progressive videos, and raster scanning, before proceeding. Some quick youtubing should suffice!
In this blog, we will try to bring the above idea into life by learning how to interface videos with FPGAs; literally, how to throw some colors on your monitor! By the end of this blog, we will design a complete video system and test it on board to see some flashing colors and a scrolling text to appreciate the effort: “YOU ARE AWESOME !”
VGA
VGA was once the most popular and de-facto interface for videos. It is still one of the most popular display standards and has come long way from the cult resolution 640 x 480p. Understanding VGA interface should set the fundamentals to dive into newer display standards like DVI, HDMI etc. Hence, choosing VGA for our video system.
VGA Monitors are driven by VGA Controller and Encoder through VGA cable. Digital side of such a display system– which we are interested in this blog–will be a VGA Controller which has to generate two set of signals: Digital pixel data and Sync signals.
Digital pixel data is typically 24-bit RGB color data, which represents a pixel, smallest entity of an image/frame in a video. Sync signals are the timing signals used by monitors to synchronize the drawing of a frame on the display. More on this here. Monitors have strict timing requirements for different video resolutions as complied by VESA Monitor Standards for vertical and horizontal synchronization. Ensuring this timing is the critical job of a VGA Controller.
VGA Controller typically drives an external Video DAC / VGA Encoder, which translates Digital RGB data to Analog RGB at required voltage level, and sent through VGA cable to the monitor. If the timings are proper and the resolution is supported, Modern monitors will automatically identify the resolution and display the video.
Design of VGA Controller
Following are the specifications of VGA Controller v1.2 (v1.1 here) which we design, refer to IP documentation for full specs:
- Generates timing for progressive videos.
- Compile-time configurable maximum resolution.
- Run-time configurable video resolution; active, blanking, sync, and polarity.
- Timing complied with VESA monitor standards.
VGA Controller v1.2 – Block Diagram
Horizontal and Vertical Counters keep count of no. of pixels in a scan line and no. of scan lines processed.
\text{Total no. of pixels in a scan line = Active video width + Blank}
\text{Total no. of scan lines in a frame = Active video height + Blank}
Blank includes Sync, Front, Back Porches which are ‘invisible’ or ‘inactive’ or blanking region of a video frame. These values can be obtained from VESA monitor standards for the target video resolution.
Based on the count, Video Enable, Hsync, Vsync, Hblank, and Vblank pulses are generated at appropriate timings at Video Timing Interface. This timing generation can be optionally synchronized with an external Frame Sync.
Video Clock is an essential aspect of VGA Controller. The frequency of Video Clock necessary to render the video in given resolution and refresh rate is given in VESA monitor standards. Or it can be calculated as:
\text{Video Clock} = N_{\text{Horizontal pixels}} * N_{\text{Scan lines}} * \text{Refresh rate}
Video Clock should be used as the system clock of VGA Controller. This clock is typically generated from a PLL for accuracy and minimal jitter. The core also supports Clock Enable, in case the user wants to use a multiple of Video Clock to clock VGA Controller. For eg: if Video Clock required is 75 \text{ MHz}, Clock Enable can be pulsed at every two clock cycles of 150 \text{ MHz} system clock to derive 75 \text{ MHz} Video Clock operation.
On-board Testing
Simulating video frames are hectic and time consuming process. And it is difficult to visualize the video being rendered. Hence, we design, synthesise, and setup a complete video test system based on VGA Controller to render a test video directly to a monitor. After all, what is more satisfactory than actually watching the video rather than simulating!
Following diagram shows the basic setup to do on-board test of VGA Controller with a test video:
VGA Controller v1.2 – Test Setup
VGA Controller generates all video timing signals and feed Data Generator. The video frame to be displayed is generated by Data Generator based on the timing signals. The text to be displayed is also stored in a small read-only Block RAM buffer inside Data Generator. Data Generator generates 12-bit pixel data, re-syncs all video timing signals, and send them to Video DAC or VGA Encoder. Most FPGA boards have inbuilt DAC. My Basys-3 has got a simple resistor based DAC in it. If using a dedicated external Video DAC like ADV7125, you may have to properly clock forward Video Clock to drive the DAC clock. The DAC can then directly drive analog VGA signals at voltage level required by a Monitor that has VGA/DVI interface.
Synthesise the video test system and download the bit file to FPGA. If you have done everything correctly, then you must be seeing something like this:
You Are Awesome !
The test was done with Basys-3 FPGA board and a Full HD monitor. The video being rendered by video test system is 720p HD.
Note: The polarity of Hsync and Vsync signals can vary across monitors. I have noticed that most monitors don’t comply with Vsync and Hsync polarities given in VESA monitor standards. If you mess up the polarity, you will simply end up with black screen or video being unrecognized by Monitor. So you may have to play around with polarities during testing to get the video displayed. Most monitors work with active-high polarity. It is also imperative that Video Clock should be accurate to produce proper video timing for Monitor.
VGA Controller v1.2 – Source Codes & User Guide
VGA Controller v1.2 is a fully tested, portable, configurable, and synthesisable soft IP core. All source codes of VGA Controller v1.2 IP are open-source licensed and can be downloaded for free from the links below. The source codes include:
- Design codes.
- Synthesisable test bench with Clock Enable for real-time on-board testing of 720p video.
- Synthesisable test bench with PLL for real-time on-board testing of 720p video.
Download VGA Controller v1.2 – IP Source Codes
Download VGA Controller v1.2 – IP User Guide
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Bonus
How to design a seven segment decoder and control seven segment displays with FPGAs? Find it out here.
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