Digital Logic Design White Papers Static Timing Analysis by Examples – using SDC By chipmunk December 14, 2024 0 5 min read: Performing STA of your RTL designs with SDC can sometimes be intimidating, especially for the beginners. Let's break it down in today's blog... Read more
Digital Logic Design Designing RISC-V CPU from scratch – Part 6: Register File By chipmunk October 4, 2024 1 10 min read: Ever fancied designing your own processor but had no idea where to start with? Part-6 of RISC-V CPU Development blog series is here... Read more
Digital Logic Design Designing RISC-V CPU from scratch – Part 5: Decode Unit By chipmunk April 6, 2024 4 10 min read: Ever fancied designing your own processor but had no idea where to start with? Part-5 of RISC-V CPU Development blog series is here... Read more
Digital Logic Design White Papers Logic vs Wire in SV – some misconceptions By chipmunk February 9, 2024 2 5 min read: How do wire vs logic compare in System Verilog? What If I said it doesn't make any sense to compare them at all! Read on... Read more