Digital Logic Design The devotion of Suspect X By chipmunk July 18, 2026 0 15 min read: Every design failure has its suspects. This time, it's X. Let's investigate where it comes from, if it's a villain of RTL simulation or an innocent messenger... Read more
Digital Logic Design Arbiters: Order in the Chaos By chipmunk February 7, 2026 0 10 min read: In a chaotic environment of multiple conflicting fights for a shared resource, the arbiter brings the order. Acting as a mediator, it observes all incoming requests and deterministically selects one requester to grant access. Read more
Digital Logic Design White Papers Static Timing Analysis by Examples – using SDC By chipmunk December 14, 2024 0 5 min read: Performing STA of your RTL designs with SDC can sometimes be intimidating, especially for the beginners. Let's break it down in today's blog... Read more
Digital Logic Design Pequeno CPU Designing RISC-V CPU from scratch – Part 6: Register File By chipmunk October 4, 2024 2 10 min read: Ever fancied designing your own processor but had no idea where to start with? Part-6 of RISC-V CPU Development blog series is here... Read more
Digital Logic Design Pequeno CPU Designing RISC-V CPU from scratch – Part 5: Decode Unit By chipmunk April 6, 2024 4 10 min read: Ever fancied designing your own processor but had no idea where to start with? Part-5 of RISC-V CPU Development blog series is here... Read more