Some of you may already know that I have been blogging a lot on the Pequeno CPU here, which I designed from scratch in RTL. The Pequeno is a 5-stage pipelined in-order RV32I processor designed to strike a balance between area and performance. After completing the design and validation, the first question, which left me pondering was: how good is the processor I have designed?
Is it “good enough” for what it was designed for?
Did it meet the performance goal?
How does my CPU compare with others?
Where are the bottlenecks hidden?
What can I improve about the pipeline of the CPU?
This whitepaper is a result of the above questions that I asked myself. In summary, this whitepaper discusses the journey of benchmarking a RISC-V processor with the industry-standard benchmark, CoreMark®.
Read the full whitepaper here
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