Digital Logic Design Micro-architecture to check Divisibility by N By chipmunk May 14, 2022 1 5 min read: How can we check that a serially received number is divisible by N? How can we design the micro-architecture for it in RTL? Read more
Digital Logic Design Designing Skid Buffers for Pipelines By chipmunk March 27, 2022 10 5 min read: What are Skid Buffers? How is it useful while designing elastic pipelines? How to design a Skid Buffer in Verilog / VHDL? Read on... Read more
Digital Logic Design Constraining IO-Reg timing paths in FPGAs By chipmunk December 18, 2021 0 5 min read: Quick guide on understanding, analyzing and constraining IO-Reg timing paths in FPGAs. Breaking down the math running behind STA tools. Read more
Digital Logic Design Debouncing Switches in Verilog / VHDL By chipmunk November 14, 2021 1 5 min read: Interfacing switches in a circuit is simple. But why my switch acts like it was pushed many times while I actually pushed it only once!? Switches are all fun until the culprit comes out ... Bouncing Read more
Digital Logic Design Latches in RTL – Why you should avoid on FPGAs By chipmunk August 15, 2021 2 5 min read: Ever modelled a D-latch in RTL and ended up working like an AND gate when tested on FPGA board? What went wrong? Why latches are not as simple as it looks like? Read on ... Read more