Digital Logic Design Latches in RTL – Why you should avoid on FPGAs By chipmunk August 15, 2021 2 5 min read: Ever modelled a D-latch in RTL and ended up working like an AND gate when tested on FPGA board? What went wrong? Why latches are not as simple as it looks like? Read on ... Read more
Digital Logic Design Clock Dividers using Flip-Flops in RTL on FPGAs – a Big NO! By chipmunk August 7, 2021 0 5 min read: Why creating or deriving clocks using RTL is a bad design practice on FPGAs? What are the alternatives? Read more