Motivation

Writing timing constraints and performing Static Timing Analysis of your RTL designs with SDC can sometimes be intimidating, especially for the beginners. I thought of breaking it down in today’s blog through simple examples you typically encounter in your design journey.

Along with the RTL, I have always made it a habit to write the timing constraints for the designs whenever I compile and synthesise the RTL on FPGAs. It enables timing analysis (STA) of the design and helps to understand how good the design is timing-performance-wise.  I have put some of my learnings into a white paper for the readers. The readers are expected to have a basic understanding of setup and hold time requirements in digital designs. If not, I suggest you to go through the references mentioned in the white paper. They have been my primary resources to learn STA by myself at the beginning of my career, and I refer to those books to date.

The white paper compiles a set of design examples with commonly encountered clocking schemes, and discusses how to write the SDC timing constraints for the clocks. Timing exceptions are also discussed with examples. Tool specific options are also discussed in some examples. The document covers only the fundamental aspects of writing timing constraints using SDC. It doesn’t go deep into the syntax, intricacies, and variations of SDC commands.

Download the full white paper here .

Happy learning!