Clocks are probably the most important and critical signals in any synchronous design. Resets are equally critical signals with high-fanout like clocks. They are routed and spread across the design elements as dense as clocks. Hence, reset design strategy is as important as clock design strategy. Resets have to be to properly asserted and removed in a design to initialize the design to a known and deterministic state after powering up.

The role of a reset controller is to ensure the proper reset sequencing in a system. In this blog, we will walk through on how to design a simple Reset Bridge or Reset Controller in RTL, which supports different configurations as required by user application.

Let’s collect some initial thoughts before proceeding to the requirements of Reset Controller…

Asynchronous External Reset

Typically, every chip has an external reset, which is most of the times, an asynchronous reset. This maybe coming from an external push-button switch or power-on reset circuit. This signal should be glitch-free to avoid inadvertent reset of the circuit during the functioning. If the reset is coming from an external push button, this signal could be glitchy due to the noise characteristics of a typical switch. This is called bouncing. Hence, the switch should be de-bounced to avoid glitches (Read about de-bouncing switches in my blog here).

Assuming, the external reset is glitch free, the next thing to consider is the synchronization of the reset to the system’s clock. In majority of the ASIC designs, assertion of the reset can be asynchronous but the de-assertion of the reset needs to be synchronized to avoid metastability (why? read about recovery and removal time of asynchronous signals here). In majority of the FPGA designs, both assertion and de-assertion of the reset are required to be synchronous. These are called fully synchronous resets.

Minimum Width of Reset

User may require that, reset should be recognized only if it has a minimum pulse width at input. Otherwise, ignore them as ‘glitches’.

Reset Sequencing

If we have a complex system rather than a simple peripheral, say, a processor-subsystem or an SoC. Different modules—Processor, Interconnect/Bus structures, Peripherals—may require their resets to be asserted together, but may have to be sequenced properly while de-asserting. In such systems, the reset may need to be remained held until all the clocks are up. A classic example is show below, where the reset to a system is held asserted until the PLL is locked and the clock is stable.

Reset in a system with PLL

In this case, the inverted PLL lock signal needs to be “ORed” with the reset input so that the reset de-assertion sequence can start safely.

Reset Controller v1.1 – Specifications

Keeping in mind the above requirements, we reach at the following specifications for Reset Controller v1.1:

• Supports asynchronous reset at primary reset input.
• Supports digital glitch filter at primary reset input.
• Supports auxiliary reset at input which is ORed with the primary reset input.
• Output reset can be configured as fully synchronous OR synchronized only at de-assertion.
• Supports daisy-chained reset outputs (RST0, RST1, RST2), which are stretched and de-asserted sequentially.

Designing the IP Architecture

Functional block diagram of Reset Controller IP looks like:

Reset Controller v1.1 – Block Diagram

Glitch filter filters out the glitches in the external reset input to the system, async_rst. It acts like a debouncer if the reset is coming from a noisy switch. The glitch filter is a digital filter and hence has separate clock and reset. This filter may be bypassed if the external reset is guaranteed to be glitch free by circuit design. If enabled, the glitch filter should be reset and initialized first before the Reset Controller IP is ready for functional operation. A “paradox” question may arise here like what if the glitch filter’s reset, gf_rst is not guaranteed to be glitchy? This may cause glitches at the filtered system reset, rst_filt. Well, gf_rst should be glitch free by circuit design. Even if it is not, the glitch filter typically runs in a slower clock than the system and uses an internally synchronized reset inside, i.e., the reset should be at least two clock cycles (gf_clk) to ensure that the filter is reset. Hence, the glitches at gf_rst will not affect the system reset.

FF Synchronizer synchronizes the external reset to the system clock domain using a chain of flip-flops. This removes any metastability of reset assertion/de-assertion.

Minimum Reset Width Validator makes sure that only reset pulses with a minimum width will be recognized for reset assertion/de-assertion. Otherwise, the reset pulse is classified and ignored as ‘glitches’.

Reset Stretcher is responsible for stretching the synchronized reset and proper reset sequencing.

Some of the techniques and codes on how to design above ‘micro-tweak’ circuits are discussed in one of my previous blogs. Find the corresponding codes here.

Configuring the IP for User Applications

The core can be configured ahead of synthesis and tuned as per the user application (refer to the User Guide for more details). For e.g., I have successfully used and tested this IP to reset a complete Microblaze based processor-subsystem implemented on Xilinx FPGA. Xilinx-recommended reset sequencing was followed for the application; sequencing of 16 clock cycles between bus interconnect, peripherals, and processor resets.

Resetting processor sub-system using Reset Controller

Reset Controller v1.1 – Source Codes & User Guide

Reset Controller v1.1 is a fully tested, portable, configurable and synthesisable soft IP core. All source codes and IP documentation of Reset Controller v1.1 are open-source and can be downloaded for free from the links below:

Download the IP package and resources from the Chipmunk IP Catalog:
IP Solutions – reset_controller_v1_1
Updates
Apr-2024: Reset Controller v1.0 has been archived and removed from the IP catalog
May-2024: Reset Controller v1.1 has been released with upgraded features!

Support

Leave a comment or visit support for any queries/feedback regarding the content of this blog.
If you liked Chipmunk , don’t forget to follow!:

Follow Chipmunk