Design of Reset Controller in Verilog / VHDL

Clocks are probably the most important and critical signals in any synchronous design. But resets are equally critical signals with high-fanout like clocks. They are routed and spread across the design elements as dense as clocks. Hence, reset design strategy is as important as clock design strategy. Resets have to be to properly asserted and removed in a design to setup the design to a known and deterministic state after powering up.

In this blog, we will walk through on how to design a simple Reset Bridge or Reset Controller in RTL, which supports variety of configurations as required by user application.

Some initial thoughts before proceeding to the requirements of Reset Controller…

Asynchronous External Reset

Typically, every chip has an external reset, which is essentially an asynchronous one; maybe coming from an external world like a push-button switch. Our design might be expecting a synchronous global reset inside. So, the external reset has to be synchronized to the design’s clock domain to avoid metastability.

Minimum Width of Reset

User may require that, reset should be recognized only if it has a minimum pulse width at input. Otherwise, ignore them as ‘glitches’.

Reset Sequencing

If we have a complex system rather than a simple peripheral, say, a processor-subsystem or an SoC. Different modules—Processor, Interconnect/Bus structures, Peripherals—may require their resets to be asserted together, but may have to be sequenced properly while de-asserting. The polarities of resets maybe different as well.

Reset Controller v1.0 – Specifications

Keeping in mind the above requirements, we reach at the following specifications for Reset Controller v1.0:

  • Supports asynchronous reset input which is synchronized to clock.
  • Configurable polarity and synchronizer for asynchronous reset input.
  • Configurable minimum width for input reset states to be recognized.
  • Both polarities supported for synchronous reset at output.
  • Supports resetting on losing phase lock with clock.
  • Supports power-on-reset on FPGAs.
  • Configurable number of resets (RST0, RST1, RST2) with configurable sequencing.

Designing the IP Architecture

Functional block diagram of Reset Controller IP looks like:

Reset Controller v1.0 - Architecture - Chipmunk Logic

Multi-flop Synchronizer synchronizes the external reset to the core clock domain using a chain of flip-flops. This removes any metastability of reset assertion/de-assertion. The external reset should be properly de-bounced (Have you read my blog yet on debouncing?) at the input for a clean reset.

Minimum Pulse Width Validator makes sure that only reset pulses with a minimum width will be recognized for reset assertion/de-assertion. Otherwise, the reset pulse is classified and ignored as ‘glitches’.

Pulse Stretcher is responsible for stretching the synchronized reset and proper reset sequencing.

Some of the techniques and codes on how to design above ‘micro tweak’ circuits are discussed in one of my previous blogs. Find the corresponding codes here.

Configuring the IP for User Applications

The core can be configured ahead of synthesis and tuned as per user application (refer to Reset Controller v1.0 – User Guide for complete details). For e.g., I have successfully used and tested this IP to reset a complete microblaze based processor-subsystem implemented on Xilinx FPGA. Xilinx-recommended reset sequencing was followed for the application; sequencing of 16 clock cycles between Peripherals, Interconnect, and Processor resets.

Reset Controller to reset a processor-subsystem

The core generates power-on reset to the design when targeted on FPGAs as most of the FPGA synthesisers support deterministic initial state for all registers on bitfile configuration, regardless of they are externally reset or not.

Reset Controller v1.0 – Source Codes & User Guide

Reset Controller v1.0 is a fully tested, portable, configurable and synthesisable soft IP core. All source codes and IP documentation of Reset Controller v1.0 are open-source and can be downloaded for free from the links below:

Download Reset Controller v1.0 – IP Source Codes

Download Reset Controller v1.0 – IP User Guide

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2 COMMENTS

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Prajit

Very informative…can u send me the password…?

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