Digital Logic Design Clock Dividers using Flip-Flops in RTL on FPGAs – a Big NO! By chipmunk August 7, 2021 0 5 min read: Why creating or deriving clocks using RTL is a bad design practice on FPGAs? What are the alternatives? Read more
IP Cores Design of UART Controller in Verilog / VHDL By chipmunk July 10, 2021 79 5 min read: How to design a simple UART Controller in RTL from requirements to implementation? Fully synthesisable and tested UART IP Core along with source codes and IP user… Read more
Announcements and Discussions Welcome to Chipmunk! By chipmunk June 28, 2021 3 New tech blog launched by Mitu Raj for everyone who loves digital logic design or front-end chip design in Verilog & VHDL. A platform to share open-source codes, and technical… Read more