Static Timing Analysis aka STA has always been one of those tricky and complex domains to deal with for a VLSI Design Engineer. While it is too vast field to talk about, I thought of picking up one of the concepts in STA and put some insight into it today.

There are basically four types of timing paths which we have to deal with and constrain in any synchronous design.

• Reg-to-Reg paths
• IO-to-IO paths
• IO-to-Reg paths
• Reg-to-IO paths

While the first two are pretty straight forward, the last two can be confusing and tricky. Since there is no reference for timing at input or output sides, these paths are left out by STA tools unless you specify input and output delay constraints. Virtual Clocks are usually used as dummy clocks to time these paths by providing a clock reference.

It is essential to understand what an STA tool expects you to provide as input delay and output delay timing constraints on IO-to-Reg and Reg-to-IO paths. And how the STA tool computes the slack and reports whether you have met timing or not. There are various factors/parameters which have to be incorporated in IO delay information expected by STA tool.

The complete picture is ‘hidden’ in most of the books/STA user guides. So I thought of digging a bit and experimenting with some example designs, and analyzed the detailed timing reports. I have finally managed to crack and simplify the math behind the timing analysis of IO-Reg paths and put this on a white paper.

The white paper demonstrates a simple scenario where an FPGA and an ASIC are communicating to each other in a system-synchronous design in a single clock domain. The timing analysis is assumed to be done in the FPGA side.

IO-Reg Timing Paths

You can freely download the white paper here.

Support

Leave a comment or visit support for any queries/feedback regarding the content of this blog.
If you liked Chipmunk , don’t forget to follow!: