Some Background Story

I have been thinking about designing a processor in RTL for a long time with the faintest idea of where to begin with. I even started with a simple ALU processor long ago i.e., one which is capable of doing some basic ALU operations. It was too crude given that it had no standardized ISA, (had to painfully create my own instruction set!) and the execution was sequential i.e., fetch, decode, and execute one instruction at a time. Then move to next instruction and so on. This is an example for a non-pipelined CPU architecture which has sequential operation. Hence, the throughput is very low. So, it was not much of an interesting project to explore and eventually the whole thing was dropped somewhere along the way…

Lately, I have been learning and exploring on ISAs, and RISC-V got most of my attention. The revolutionary ISA hit the market like tidal waves with relentless innovations backed up by countless learning and tool resources, and contributions from around the engineering community. And the ultimate beauty of RISC-V is being an open-source ISA. So, I thought: why not get on the bandwagon!?

Eventually, the idea converged from “Designing a Processor” to “Designing a RISC-V Processor“. The pain of defining your own instruction set is gone now! But a little pain is good for learning. Hence, let’s expand the idea to: “Designing a Pipelined RISC-V Processor“.

Over the next few weeks, I will be demonstrating how to bring this idea to life through the new RISC-V CPU Development blog series which will be published here in multiple parts. We will go through defining specs, designing and refining architecture, identifying and solving challenges, developing RTL, implementing, and testing the CPU on simulation/FPGA board.

Disclaimer: All the idea to be presented in the blog series, are things I learnt on the way with my “baby steps” by exploring different RTL implementations, standards, documentations of proven RISC-V processors. The architectures presented in the blog are fundamental and the designed CPU is purely for education purpose. Industrial CPU architectures are way more complex beyond the scope of this blog.

Step 1: Naming the CPU

Naming or branding your idea is mandatory to keep you motivated moving forward until you reach the goal! We are going to build a quite simplistic processor, so I came up with this fancy name “Pequeno“, which means “tiny” in Spanish; the complete name: Pequeno RISC-V CPU aka PQR5. Through out the blog series, I will be using this name… 🙂

Step 2: Picking up the ISA

RISC-V has different flavors & extensions in the ISA. Let’s go with the simplest one. RV32I aka 32-bit Base Integer ISA. The ISA is suitable to build a 32-bit CPU which supports integer arithmetic. So here comes the first spec of Pequeno:

Pequeno is a 32-bit RISC-V CPU which supports RV32I ISA.

Step 3: Getting hold of the ISA

RV32I has 37 base instructions of 32-bit, which we plan to implement in Pequeno. So it’s imperative that we should have deep understanding of each instruction. I went the hard way to get complete hold of the ISA. I learned the full spec and designed my own assembler, pqr5asm, in the process and validated it against some of the popular RISC-V assemblers.

RISBUJ

The above six letter word summarizes the types of instructions in RV32I. The 37 instructions fall under one of the categories:

• R-type: All integer computation instructions on registers.
• I-type: All integer computation instructions on registers and immediate values. Also includes JALR, Load instructions.
• S-type: All Store instructions.
• B-type: All Branch instructions.
• U-type: Special instructions like LUI, AUIPC.
• J-type: Jump instructions like JAL.

32 general purpose registers are available in RISC-V architectures, \text{x0-x31} . All registers are 32-bit. Among these 32 registers, zero aka \text{x0} register is a useful special register hardwired to zero, it cannot be written, and is always read as zero. So what is the use of it? You can use \text{x0} as dummy target to dump results you don’t care to read, or use as operand zero, or generating NOP instructions to idle CPU.

This Integer computations instructions are ALU instructions performed on register(s) and/or 12-bit immediate values. Load/Store instructions perform storing/loading data between registers and data memory. Jump/Branch instructions are used to transfer the control of program to different location.

Detailed information on each instruction can be found in the RISC-V spec: RISC-V User-Level ISA v2.2
To learn the ISA, the RISC-V spec docs are enough. However, to clarify you can look into the implementation of different open cores in RTL.

Apart from 37 base instructions, I have also added 13 pseudo/custom instructions to pqr5asm and extended the ISA to 50 instructions. These instructions are derived from base instructions and are there to make assembly programmer’s life easier… An e.g is: \text{NOP} instruction which is same as \text{ADDI x0, x0, 0} which of course does NOTHING in CPU! But it is simpler and easier to interpret in the code.

The expectation before we start designing the processor architecture is the complete understanding of how each instruction is encoded in 32-bit binary and what is its functionality.

RISC-V Instruction – Encoding (ref: User-Level ISA v2.2)

PQR5ASM – Assembler for Pequeno

PQR5ASM, the RISC-V RV32I assembler which I developed in Python is available in my github here. You can write sample assembly code taking reference from Assembler Instruction Manual. Compile it, and see how it translates to 32-bit binary to cement/verify your understanding before moving on further…

Whenever you are ready, stay tuned for the next blog in the RISC-V CPU Development series! 🙂

Visit the complete blog series

This post is part of RISC-V CPU Development blog series 

|~~~~ J U M P ~~ T O ~~~~| Next part >>

Support

Leave a comment or visit support for any queries/feedback regarding the content of this blog.
If you liked Chipmunk , don’t forget to follow!: