2021 – Chipmunk Logic

Constraining IO-Reg timing paths in FPGAs

By chipmunk December 18, 2021 0

5 min read: Quick guide on understanding, analyzing and constraining IO-Reg timing paths in FPGAs. Breaking down the math running behind STA tools.

Digital Logic Design

Debouncing Switches in Verilog / VHDL

By chipmunk November 14, 2021 1

5 min read: Interfacing switches in a circuit is simple. But why my switch acts like it was pushed many times while I actually pushed it only once!? Switches are all fun until the culprit comes out ... Bouncing

IP Cores

Design of Reset Controller in Verilog / VHDL

By chipmunk September 19, 2021 2

5 min read: Resets are critical in your design! De-mystify resets and understand how to design a Reset Controller in RTL from scratch. Download the open-source Reset Controller IP for free.

Digital Logic Design

Latches in RTL – Why you should avoid on FPGAs

By chipmunk August 15, 2021 2

5 min read: Ever modelled a D-latch in RTL and ended up working like an AND gate when tested on FPGA board? What went wrong? Why latches are not as simple as it looks like? Read on ...

Digital Logic Design

Clock Dividers using Flip-Flops in RTL on FPGAs – a Big NO!

By chipmunk August 7, 2021 0

5 min read: Why creating or deriving clocks using RTL is a bad design practice on FPGAs? What are the alternatives?

Year: 2021