IP Cores Designing an SPI based Programmable Seven Segment Decoder in RTL By chipmunk November 16, 2022 2 5 min read: Seven segment displays are cumbersome to interface and drive, yet so useful. How about simplifying the problem by designing your own programmable Seven Segment Decoder in Verilog/VHDL? Read more
Digital Logic Design Adding M-bit numbers N times By chipmunk September 24, 2022 0 5 min read: Numbers of length M-bit have to be added N times. What should be the min size of the accumulator which can store the sum without any overflow/redundancy? Read on... Read more
Digital Logic Design Designing Memory-mapped Peripheral IPs in RTL By chipmunk July 29, 2022 4 10 min read: Developing an IP in RTL? How can you transform your IP in bare RTL into a simple memory-mapped peripheral (APB/AXI ...) for SoC integration? Read on ... Read more
Digital Logic Design Micro-architecture to check Divisibility by N By chipmunk May 14, 2022 1 5 min read: How can we check that a serially received number is divisible by N? How can we design the micro-architecture for it in RTL? Read more
Digital Logic Design Designing Skid Buffers for Pipelines By chipmunk March 27, 2022 10 5 min read: What are Skid Buffers? How is it useful while designing elastic pipelines? How to design a Skid Buffer in Verilog / VHDL? Read on... Read more