IP Cores Designing an SPI based Programmable Seven Segment Decoder in RTL By chipmunk November 16, 2022 2 5 min read: Seven segment displays are cumbersome to interface and drive, yet so useful. How about simplifying the problem by designing your own programmable Seven Segment Decoder in Verilog/VHDL? Read more
IP Cores Displaying Videos with VGA Controller in Verilog / VHDL By chipmunk January 9, 2022 22 5 min read: Fancy displaying some colors and video patterns on your monitor with FPGA? Learn how to design a simple VGA Controller in RTL and get grasp on basics of video interfacing with FPGAs/ASICs. Read more
IP Cores Design of Reset Controller in Verilog / VHDL By chipmunk September 19, 2021 2 5 min read: Resets are critical in your design! De-mystify resets and understand how to design a Reset Controller in RTL from scratch. Download the open-source Reset Controller IP for free. Read more
IP Cores Design of UART Controller in Verilog / VHDL By chipmunk July 10, 2021 79 5 min read: How to design a simple UART Controller in RTL from requirements to implementation? Fully synthesisable and tested UART IP Core along with source codes and IP user guide for free download. Read more