Digital Logic Design Designing RISC-V CPU from scratch – Part 3: Dealing with Pipeline Hazards By chipmunk July 8, 2023 4 5 min read: Ever fancied designing your own processor but had no idea where to start with? Part-3 of RISC-V CPU Development blog series is here... Read more
Digital Logic Design Designing RISC-V CPU from scratch – Part 2: Specifications & Architecture By chipmunk April 30, 2023 6 5 min read: Ever fancied designing your own processor but had no idea where to start with? Part-2 of RISC-V CPU Development blog series is here... Read more
Digital Logic Design Designing RISC-V CPU from scratch – Part 1: Getting hold of the ISA By chipmunk April 7, 2023 3 5 min read: Ever fancied designing your own processor but had no idea where to start with? Let's design a RISC-V Processor from scratch in RTL... Read more
IP Cores Designing an SPI based Programmable Seven Segment Decoder in RTL By chipmunk November 16, 2022 2 5 min read: Seven segment displays are cumbersome to interface and drive, yet so useful. How about simplifying the problem by designing your own programmable Seven Segment Decoder in Verilog/VHDL? Read more
Digital Logic Design Adding M-bit numbers N times By chipmunk September 24, 2022 0 5 min read: Numbers of length M-bit have to be added N times. What should be the min size of the accumulator which can store the sum without any overflow/redundancy? Read on... Read more