Digital Logic Design Designing Memory-mapped Peripheral IPs in RTL By chipmunk July 29, 2022 2 10 min read: Developing an IP in RTL? How can you transform your IP in bare RTL into a simple memory-mapped peripheral (APB/AXI ...) for SoC integration? Read on ... Read more
Digital Logic Design Micro-architecture to check Divisibility by N By chipmunk May 14, 2022 1 5 min read: How can we check that a serially received number is divisible by N? How can we design the micro-architecture for it in RTL? Read more
Digital Logic Design Designing Skid Buffers for Pipelines By chipmunk March 27, 2022 10 5 min read: What are Skid Buffers? How is it useful while designing elastic pipelines? How to design a Skid Buffer in Verilog / VHDL? Read on... Read more
IP Cores Displaying Videos with VGA Controller in Verilog / VHDL By chipmunk January 9, 2022 22 5 min read: Fancy displaying some colors and video patterns on your monitor with FPGA? Learn how to design a simple VGA Controller in RTL and get grasp on basics of video interfacing with FPGAs/ASICs. Read more
Digital Logic Design Constraining IO-Reg timing paths in FPGAs By chipmunk December 18, 2021 0 5 min read: Quick guide on understanding, analyzing and constraining IO-Reg timing paths in FPGAs. Breaking down the math running behind STA tools. Read more