IP Cores Displaying Videos with VGA Controller in Verilog / VHDL By chipmunk January 9, 2022 22 5 min read: Fancy displaying some colors and video patterns on your monitor with FPGA? Learn how to design a simple VGA Controller in RTL and get grasp on basics of video interfacing with FPGAs/ASICs. Read more
Digital Logic Design White Papers Constraining IO-Reg timing paths in FPGAs By chipmunk December 18, 2021 0 5 min read: Quick guide on understanding, analyzing and constraining IO-Reg timing paths in FPGAs. Breaking down the math running behind STA tools. Read more
Digital Logic Design Debouncing Switches in Verilog / VHDL By chipmunk November 14, 2021 1 5 min read: Interfacing switches in a circuit is simple. But why my switch acts like it was pushed many times while I actually pushed it only once!? Switches are all fun until the culprit comes out ... Bouncing Read more
IP Cores Design of Reset Controller in Verilog / VHDL By chipmunk September 19, 2021 2 5 min read: Resets are critical in your design! De-mystify resets and understand how to design a Reset Controller in RTL from scratch. Download the open-source Reset Controller IP for free. Read more
Digital Logic Design Latches in RTL – Why you should avoid on FPGAs By chipmunk August 15, 2021 2 5 min read: Ever modelled a D-latch in RTL and ended up working like an AND gate when tested on FPGA board? What went wrong? Why latches are not as simple as it looks like? Read on ... Read more